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  1. N. Taheri, S. Tabrizchi, Sh. Angizi, and A. Roohi*, “ChaoSen: Security Enhancement of Image Sensor through in-Sensor Chaotic Computing,” 42nd IEEE International Conference on Computer Design (ICCD), Milan, Italy, 2024.
  2. R. Gaire, S. Tabrizchi, D. Najafi, Sh. Angizi, and A. Roohi*, “DECO: Dynamic Energy-aware Compression and Optimization for In-Memory Neural Networks,” IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), August 11-14, 2024.
  3. R. Gaire, S. Tabrizchi, and A. Roohi*, “Resource-Efficient Adaptive-Network Inference Framework with Knowledge Distillation-based Unified Learning,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 1-2, 2024.
  4. M. Morsali, R. Velpula, M. Muthu, H. Nguyen, M. Imani, A. Roohi, R. Zand, and Sh. Angizi*, “Energy-Efficient Near-Sensor Event Detector based on Multilevel Ga2O3 RRAM,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 1-2, 2024.
  5. N. Taheri, S. Tabrizchi, D. Najafi, Sh. Angizi, and A. Roohi*, “ResSen: Imager Privacy Enhance- ment through Residue Arithmetic Processing in Sensors,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 1-2, 2024.
  6. D. Najafi, S. Tabrizchi, R. Zhou, M. Solouki, A. Marshal, A. Roohi, and Sh. Angizi*, “Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing,” ACM Great Lakes Symposium on VLSI (GLSVLSI 2024), June 12-14, 2024.
  7. S. Tabrizchi, N. Taheri, Sh. Angizi, and A. Roohi*, “RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security,” ACM Great Lakes Symposium on VLSI (GLSVLSI 2024), June 12-14, 2024.
  8. B. Reidy, S. Tabrizchi, M. Mohammadi, Sh. Angizi, A. Roohi, and R. Zand*, “HiRISE: High- Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI,” 61st Design Automation Conference (DAC), San Francisco, CA, USA, July 23-27, 2024.
  9. M. Morsali, B. Reidy, D. Najafi, S. Tabrizchi, M. Imani, M. Nikdast, A. Roohi, R. Zand, and Sh. Angizi*, “Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing,” 61st Design Automation Conference (DAC), San Francisco, CA, USA, July 23-27, 2024.
  10. S. Tabrizchi, Sh. Angizi, and A. Roohi*, “DIAC: Design Exploration of Intermittent-Aware Com- puting Realizing Batteryless Systems,” 44th Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, 25 – 27 March 2024.
  11. M. Morsali, S. Tabrizchi, D. Najafi, M. Imani, M. Nikdast, A. Roohi, Sh. Angizi*, “OISA: Archi- tecting an Optical In-Sensor Accelerator for Efficient Visual Computing,” 44th Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, 25 – 27 March 2024.
  12. R. Zhou, S. Ahmed, A. Roohi, A. Rakin, and Sh. Angizi*, “DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks,” 44th Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, 25 – 27 March 2024.
  13. M. Morsali, S. Tabrizchi, M. Liehr, N. Cady, M. Imani, A. Roohi, and Sh. Angizi*, “Deep Mapper: A Multi-Channel Single-Cycle Near-Sensor DNN Accelerator,” IEEE International Conference on Rebooting Computing (ICRC), December 5-6, 2023.
  14. R. Gaire, S. Tabrizchi, and A. Roohi*, “EnCoDe: Enhancing Compressed Deep Learning Models through Feature Distillation and Informative Sample Selection,” IEEE 22nd International Conference on Machine Learning and Applications (ICMLA), December 15-17, 2023.
  15. S. Tabrizchi, Sh. Angizi, and A. Roohi*, “Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 7-8, 2023. (Best Paper Candidate)
  16. D. Vungarala, M. Morsali, S. Tabrizchi, A. Roohi, and Sh. Angizi*, “Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges,” IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), August 6-9, 2023.
  17. S. Tabrizchi, R. Gaire, Sh. Angizi, and A. Roohi*, “SenTer: A Reconfigurable Processing-in- Sensor Architecture Enabling Efficient Ternary MLP,” 33rd ACM Great Lakes Symposium on VLSI (GLSVLSI 2023), June 5-7, 2023.
  18. S. Tabrizchi, M. Morsali, Sh. Angizi, and A. Roohi*, “NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors,” 24th IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, California, May 21-25, 2023.
  19. M. Morsali, R. Zhou, S. Tabrizchi, A. Roohi*, and Sh. Angizi*, “XOR-CiM: An Efficient Computing- in-SOT-MRAM Design for Binary Neural Network Acceleration,” 24th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, April 5-7, 2023.
  20. R. Zhou, S. Tabrizchi, A. Roohi, and Sh. Angizi*, “P-PIM: A Parallel Processing-in-DRAM Framework Enabling RowHammer Protection,” 43rd Design, Automation and Test in Europe Conference (DATE), Antwerp, BE, 2023.
  21. A. Minhaz, A. Roohi*, N. Cady, and Sh. Angizi*, “A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (ESWEEK CASES), 2022.
  22. S. Tabrizchi, Sh. Angizi, and A. Roohi*, “TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes,” 40th IEEE International Conference on Computer Design (ICCD), Lake Tahoe, USA, 2022.
  23. R. Zhou, S. Tabrizchi, A. Roohi*, and Sh. Angizi*, “ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation,” 41st IEEE/ACM International Conference on Computer- Aided Design (ICCAD), San Diego, California, USA, 2022.
  24. A. Nezhadi, Sh. Angizi, and A. Roohi*, “semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training,” 21st IEEE International Conference on Machine Learning and Applications (ICMLA), 2022.
  25. S. Tabrizchi, Sh. Angizi, and A. Roohi*, “Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell,” IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4. IEEE, 2022.
  26. M. Alali, A. Roohi, J. S. Deogun*, “Enabling efficient training of convolutional neural networks for histopathology images,” International Conference on Image Analysis and Processing, pp. 533-544. Springer, Cham, 2022.
  27. R. Zhou, A. Roohi, D. Misra, and Sh. Angizi*, “FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Boston, USA, 2022.
  28. A. Roohi*, and Sh. Angizi, “Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, USA, 2022.
  29. S. Tabrizchi, Sh. Angizi, and A. Roohi*, “SCiMA: a Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations,” 23rd IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, May 28- June 1, 2022.
  30. A. Nezhadi, Sh. Angizi, and A. Roohi*, “EaseMiss: HW/SW Co-Optimization for Efficient Large Matrix-Matrix Multiply Operations,” 15th IEEE Dallas Circuit And System Conference (DCAS), pp. 1-6. IEEE, 2022.
  31. Sh. Angizi*, and A. Roohi*, “Integrated Sensing and Computing using Energy-Efficient Magnetic Synapses,” 23rd IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, April 6-8, 2022.
  32. A. Roohi*, Sh. Angizi, P. Navaeilavasani, and M. Taheri, “ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations,” 23rd IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, April 6-8, 2022.
  33. A. Roohi*, M. Taheri, Sh. Angizi, D. Fan, “RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,” 40th International Conference On Computer-Aided Design (ICCAD), 2021, pp. 1-9
  34. Sh. Angizi*, A. Roohi*, M. Taheri, D. Fan, “Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study,” 31st ACM Great Lakes Symposium on VLSI (GLSVLSI 2021), June 22-25, 2021.
  35. N. Khoshavi, S. Sargolzaei, Y. Bi, A. Roohi*, “Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network,” 26th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan.18-21, 2021.
  36. A. Roohi*, “Normally-Off Computing Design Methodology Using Spintronics: From Devices to Architectures,” International Green and Sustainable Computing Conference, October 19-22, 2020
  37. N. Khoshavi*, C. Broyles, Y. Bi, A. Roohi, “Fiji-FIN: A Fault Injection Framework on Quantized Neural Network Inference Accelerator,” IEEE International Conference on Machine Learning and Applications (ICMLA), October 19-22, 2020.
  38. N. Khoshavi*, A. Roohi, Y. Bi, “Hardware-assisted Black-box Adversarial Attack Evaluation Framework on Binarized Neural Network,” 41st IEEE Symposium on Security and Privacy, Short Talks, URL: https://www.ieee-security.org/TC/SP2020/program-shorttalks.html, 2020.
  39. N. Khoshavi*, A. Roohi*, C. Broyles, S. Sargolzaei, Y. Bi, D. Z. Pan, “SHIELDeNN: Online Accel- erated Framework for Fault-Tolerant Deep Neural Network Architectures,” 57th Design Automation Conference (DAC), San Francisco, CA, USA, July 19-23, 2020.
  40. N. Khoshavi*, A. Roohi, S. Sargolzaei, C. Broyles, and Y. Bi, “Entropy-Based Modeling for Esti- mating Soft Errors Impact on Binarized Neural Network Inference,” arXiv preprint arXiv:2004.05089 2020.
  41. A. Roohi*, and R. F. DeMara, “IRC: Cross-layer design exploration of Intermittent Robust Computation units for IoTs,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida, U.S.A., July 15-17, 2019.
  42. A. Roohi*, Sh. Angizi, D. Fan, and R. F. DeMara, “Processing-In-Memory Acceleration of Convo- lutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience,” 20th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 6-7, 2019. (Best Paper Candidate)
  43. A. Roohi*, R. Zand, and R. F. DeMara, “Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design,” 28th ACM Great Lakes Symposium on VLSI (GLSVLSI 2018), Chicago, Illinois, USA, May 23-25, 2018. (Best Paper Candidate)
  44. A. Roohi*, R. Zand, and R. F. DeMara, “Synthesis of Normally-Off Boolean Circuits: An Evolu- tionary Optimization Approach Utilizing Spintronic Devices,” The 19th International Symposium on Quality Electronic Design, Santa Clara, CA, USA, ISQED 2018. (Best Paper Candidate)
  45. R. F. DeMara*, A. Roohi, R. Zand, and S. D. Pyle, “Heterogeneous Technology Configurable Fabrics for Field Programmable Co-design of CMOS and Spin-based Devices,” in Proceedings of IEEE International Conference on Rebooting Computing (ICRC-2017), Washington, DC, USA, November 8 – 9, 2017.
  46. A. Roohi*, L. Wang, S. Kose, and R. F. DeMara, “Secure Intermittent-Robust Computation for Energy Harvesting Device Security and Outage Resilience,” The 14th IEEE International Conference on Advanced and Trusted Computing, San Francisco, CA, USA, ATC 2017.
  47. A.M.Chabi, A. Roohi, H. Khademolhosseini, Sh. Angizi, R. F. DeMara, and K. Navi*, “Cost- Efficient QCA Reversible Combinational Circuits Based on a New Reversible Gate,” The 18th CSI Symposium on Computer Architecture & Digital Systems, Tehran, Iran, CADS 2015 (Best Paper Candidate).
  48. R. A. Ashraf, A. Al-Zahrani, N. Khoshavi, R. Zand, S. Salehi, A. Roohi, M. Lin, and R. F. DeMara*, “Reactive Rejuvenation of CMOS Logic Paths using Self-Activating Voltage Domains,” IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, ISCAS 2015.
  49. A. Roohi*, R. F. DeMara, and N. Khoshavi, “Dual Computational Layer Based Logic Design for QCA Circuits,” 52nd Design Automation Conference (DAC), Work-in-Progress Session, San Francisco, CA, USA, DAC-WIP 2015.
  50. S. Sayedsalehi*, and A. Roohi, “Modeling an Improved Modified Type in Metallic Quantum-dot Fixed Cell for Nano Structure Implementation,” 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing, Turku, Finland, PDP 2015.
  51. S. Sayedsalehi*, A. Roohi, H. Khademolhosseini, and M. Kamrani, “Design of Nanoelectronic Circuits Using an Efficient Reversible Gate,” 9th International Nanotechnology Symposium, Dresden, Germany, Nanofair 2012.
  52. A. Roohi*, H. Khademolhosseini, S. Sayedsalehi, and K. Navi, ‘‘Implementation of Reversible Logic Design in Nanoelectronics on Basis of Majority Gates,” The 16th CSI Symposium on Computer Architecture & Digital Systems, Shiraz, Iran, CADS 2012.
  53. A. Roohi*, M. Kamrani, S. Sayedsalehi, and K. Navi, ‘‘A Combinational Logic Optimization for Majority Gate-Based Nanoelectronic Circuits Based on GA,” International Semiconductor Device Research Symposium, The University of Maryland, USA, ISDRS 2011.
  54. H. Khademolhosseini and A. Roohi*, ‘‘A New Redundant Method on Representing Numbers with Moduli Set {3n, 3n − 1, 3n − 2 ” Computer, Communication and Electrical Technology (ICCCET 2011), IEEE International Conference on, pp. 163-166, 2011.